MS/MBA Candidate at the University of Virginia.
I'm Michael Shires, a graduate student at the University of Virginia. I'm enrolled in a dual master's program, pursuing an MBA at the Darden Graduate School of Business and an M.S. in Computer Engineering at the School of Engineering and Applied Science.
Before this, I spent ten years in the nuclear submarine community. I trained as an Engineering Laboratory Technician (ELT) at Nuclear Power Training Unit — Ballston Spa, New York, and was then stationed on the PCU Indiana, SSN 789 in Norfolk, VA. Indiana commissioned in the fall of 2018, and we moved to Connecticut. After finishing my tour on the Indiana, I received orders to NPTU — Charleston as an instructor.
An empirical framework that surfaces high-impact instruction-fusion candidates through three complementary profiling strategies — consecutive-pair frequency, last-level-cache-miss backslices, and ROB-saturation dependency chains — evaluated on SPEC CPU 2017 with Intel APX as a case study.
Extends the PIMeval-PIMbench simulator with a configurable three-tier ECC hierarchy and a Monte Carlo tool for area, latency, and reliability tradeoffs, showing that scratchpad-ECC granularity dominates overhead across nine PIMbench workloads on a BITSIMD-V device.